#define F_CPU 8000000UL
#include <avr/io.h>
#include <avr/interrupt.h>
#include <util/delay.h>
#include <compat/deprecated.h>
void initialize(void);void init_pwm_right(void);
void start_pwm_right(void);
void stop_pwm_right(void);void init_pwm_left(void);
void start_pwm_left(void);
void stop_pwm_left(void);
int main(void)
{
volatile int i = 0, j = 0, k = 0;
initialize();
while(1) {
i = bit_is_set(PINB, PB0);
if(!i)
{ stop_pwm_left();
stop_pwm_right();
start_pwm_right();
}
else
{ stop_pwm_left();
stop_pwm_right();
start_pwm_left();
} for(j=0;j<255;j++)
{
for(k=0;k<255;k++)
{
}
}
}
}
void initialize()
{
init_pwm_left();
init_pwm_right();
start_pwm_left();
start_pwm_right();
DDRB |= (0 << DDB0);}
void init_pwm_right(void)
{
TCCR2 |= 1 << CS22; TCCR2 |= 1 << CS21; TCCR2 |= 0 << CS20;
TCCR2 |= 1 << WGM20; TCCR2 |= 1 << WGM21;
TCCR2 |= 0 << COM20; TCCR2 |= 1 << COM21; OCR2 = 255; DDRD |= (1 << DDD7);}
void init_pwm_left(void)
{
TCCR0 |= 1 << CS02; TCCR0 |= 0 << CS01; TCCR0 |= 0 << CS00;
TCCR0 |= 1 << WGM00; TCCR0 |= 1 << WGM01;
TCCR0 |= 0 << COM00; TCCR0 |= 1 << COM01; OCR0 = 255; DDRB |= (1 << DDB3);}
void start_pwm_right(void)
{
TCCR2 |= (1 << CS22); TCCR2 |= (1 << CS21); TCCR2 |= (0 << CS20);}
void start_pwm_left(void)
{
TCCR0 |= (1 << CS02); TCCR0 |= (0 << CS01); TCCR0 |= (0 << CS00);}
void stop_pwm_right(void)
{
TCCR2 &= ~(1 << CS22); TCCR2 &= ~(1 << CS21); TCCR2 &= ~(1 << CS20);}
void stop_pwm_left(void)
{
TCCR0 &= ~(1 << CS02); TCCR0 &= ~(1 << CS01); TCCR0 &= ~(1 << CS00);}